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| ds080 (v1.4) january 3, 2002 www.xilinx.com 1 advance product specification 1-800-255-7778 ? 2002 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? system-level features: - high-capacity pre-engineered configuration solution for fpgas - chipset configuration solution: ace ? controller ? configuration manager ace flash ? high-capacity compactflash ? storage device - non-volatile system solution - flexible configuration interfaces - system configuration rates of up to 30 mb/s - board space requirement as low as 25 cm 2 ace flash (xilinx-supplied flash cards): - densities of 128 mbits and 256 mbits - compactflash type i form factor - pc card ata protocol compatible - noiseless and low cmos power - automatic error correction and write retry capabilities - multiple partitions - program/erase over full commercial/industrial temperature range - removable storage device - excellent quality and reliability mtbf >1,000,000 hours minimum 10,000 insertions ace controller: - compactflash interface supports ace flash cards, standard third-party compactflash (type i or type ii) cards, and ibm microdrives with up to 8 gbit capacity - configuration of a target fpga chain through ieee 1149.1 jtag with a throughput up to 16.7 mbits/sec - interfaces include compactflash, jtag, and mpu - mpu interface is compatible with microprocessor/ microcontroller bus interfaces, such as the ibm ppc405, and siemens 80c166 - ieee 1149.1 boundary-scan standard compliant (jtag) - fat12/16 file system - compact 144-pin tqfp package -low power general description xilinx developed the system advanced configuration envi- ronment (system ace) family to address the need for a space-efficient, pre-engineered, high-density configuration solution for systems with multiple fpgas. system ace technology is a ground-breaking in-system programmable configuration solution that provides substantial savings in development effort and cost per bit over traditional prom and embedded solutions for high-capacity fpga systems. the system ace family combines xilinx expertise in config- uration control with industry expertise in commodity memo- ries. the first member of the system ace family uses compactflash. as shown in figure 1 , the system ace compactflash solu- tion is a chipset, consisting of a controller device (ace con- troller) and a compactflash storage device (ace flash). 0 system ace compactflash solution ds080 (v1.4) january 3, 2002 00 advance product specification r figure 1: system ace chipset interface to fpga target chain from compactflash, mpu, or test jtag port ace flash compactflash storage device ds080_01_032101 128 mbits or 256 mbits system ace controller device
system ace compactflash solution 2 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r figure 2 shows that the ace controller contains multiple interfaces, including compactflash, mpu, and jtag, to allow for a highly flexible configuration solution. for added flexibility, a compactflash or ibm microdrive storage device such as the xilinx ace flash card can be used to store mul- tiple bitstreams, with a capacity of up to 256 mbits. the combination of the ace controller and a standard com- pactflash or ibm microdrive storage device delivers a pow- erful configuration solution for high-density fpga systems. ace flash memory card the xilinx ace flash memory card is a compactflash solid-state storage device that complies with the personal computer memory card international association ata (pcmcia ata) specification. the ace flash card is avail- able in two densities: 128 mbits and 256 mbits. this card contains an on-card intelligent controller that manages interface protocols, data storage and retrieval, ecc, defect handling and diagnostics, power management, and clock control. using commercially available, low-cost peripheral devices, the ace flash card can be programmed independently in a pc environment, in which the flash card appears as an additional hard drive. besides these standard options, the system ace solution allows for in-system programming of an ace flash card through the ace controller mpu inter- face. the ace flash card also interfaces directly with the ace controller to provide a powerful pre-engineered configura- tion solution. see figure 3 . figure 2: ace controller interfaces mpu interface boundary-scan test tools pc-based tools embedded mpu automatic test equipment fpga target chain ds080_02_032201 configuration jtag interface (cfgjtag) test jtag interface (tstjtag) compactflash interface ace flash, third party compactflash, or ibm microdrive system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 3 advance product specification 1-800-255-7778 r system ace file structure the system ace file structure setup allows ace flash memory not used for configuration storage to be used as scratchpad memory for other system storage needs. the ability to store multiple bitstreams empowers designers to use a single ace flash card to run bist patterns, pci applications, or store multiple bitstream variations of a design (for example, versions for different geographical regions). the file structure also gives designers the flexibility to store supporting information with the bitstreams in addition to configuration data, such as release notes, user guides, faqs, or other supporting files. figure 3: ace flash card block diagram ds080_03_032101 compactflash internal single chip controller host interface data in/out compactflash modules control table 1: ace flash card capacity specifications capacity (bits) sectors/card (max lba+1) number of heads number of sectors/tracks number of cylinders 128,450,560 31,360 2 32 490 256,901,120 62,720 4 32 490 system ace compactflash solution 4 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r ace controller the ace controller manages fpga configuration data. the controller provides an intelligent interface between an fpga target chain and various supported configuration sources; it can target multiple fpga devices using jtag at a selectable throughput of up to 16.7 mbits/sec. as shown in figure 4 , three interfaces are available for configuring a tar- get fpga chain through the configuration jtag port. these interfaces are: compactflash, microprocessor (mpu), and test jtag. the directory structure used by the ace controller enables it to support both compactflash and ibm microdrive devices through the compactflash port. the mpu interface has access to the compactflash port, the configuration jtag port, and local control/status fea- tures. the test jtag port is used when doing bound- ary-scan testing of the target fpga chain or the ace controller. details about each interface are discussed below. the ace controller has two main power supplies: the core power supply (v ccl ) and a compactflash/test jtag inter- face power supply (v cch ). the v cch power source supplies the test jtag and compactflash port levels. these two interfaces must be powered at 3.3v. the v ccl core power source supplies the mpu and configuration jtag ports, which can be run at 3.3v or 2.5v. it is important to note that these two interfaces are always powered at the same volt- age. considerations for the interface voltage are discussed in typical configuration modes , page 35 . see figure 5 . figure 4: system ace controller block diagram ds080_04_030801 compactflash port mpu port test jtag (tstjtag) port configuration jtag (cfgjtag) port configuration jtag controller compactflash arbiter mpu control and status compactflash controller misc. (leds, etc.) test scan jtag interface (target fpga chain) system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 5 advance product specification 1-800-255-7778 r status indicators the ace controller has indicator pins to help monitor device status during operation. figure 5: ace controller i/o requirements ds080_05_030801 compactflash core cfgjtag mpu tstjtag ls ls ls ls ls ls shaded output buffers drive v oh = v ccl = 2.5v or 3.3v s shaded input buffers sense v ih = v ccl = 2.5v or 3.3v s all non-shaded output buffers drive v oh = v cch = 3.3v s all non-shaded input buffers sense v ih = v cch = 3.3v s "ls" denotes level-shifter s core voltage level = v ccl = 2.5v or 3.3v s table 2: ace controller status indicators name pin description statled 95 when on, the status led indicates that configuration is done. when blinking, this led indicates that configuration is still in progress. when off this led indicates that configuration is in an idle state. errled 96 when on, the error led indicates that an error occurred. when blinking, this led indicates that no compactflash device was found when the compactflash for the configuration jtag interface was enabled. when off, this led indicates that no errors are detected. system ace compactflash solution 6 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r system ace reset notes: 1. when using the system ace controller reset, tsreset + twreset of three rising edges of clk is required. figure 6: system ace reset function timing diagram cycle clk reset cycle 0 cycle 1 cycle 2 cycle 3 tsreset threset twreset ds080_56_071801 table 3: system ace reset symbol parameter min max units tw(reset) system ace controller reset pulse width 3 (1) rising edges th(reset) reset hold time after rising edge of clk 0 ns ts(reset) system ace controller reset setup up time before rising edge of clk 7 (1) ns system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 7 advance product specification 1-800-255-7778 r interfaces overview this section discusses the details of each supported ace controller interface. compactflash interface (cf) the compactflash interface is the key ace controller inter- face for high-capacity systems. the compactflash port can accommodate xilinx ace flash cards, any standard com- pactflash module, or ibm microdrives up to 8 gbits, all with the same form factor and board space requirements. the use of standard compactflash devices gives system designers access to high-density flash in a very efficient footprint that does not change with density. compactflash is a removable medium, which makes changes and/or upgrades to the memory contents or density simple. the compactflash interface is comprised of two pieces: a compactflash controller, and a compactflash arbiter. the compactflash controller detects the presence and main- tains the status of the compactflash device. this controller also handles all compactflash device access bus cycles, and abstracts and implements compactflash commands such as soft reset, identify drive, and read/write sector(s). the compactflash arbiter controls the interface between the mpu and the configuration jtag controller for access to the compactflash data buffer. compactflash devices are compliant with multiple read and write modes. the system ace configuration controller supports ata common memory read and write functions specifically. figure 7 and figure 8 provide detailed timing information on these functions. figure 7: ace flash ata memory write timing diagram ds080_09_031301 address address reg reg din din ce ce we we wait wait t v (wt-we) (wt-we) din valid din valid t v (wt) (wt) t su su (a) (a) t su su (ce) (ce) t w (we) (we) t w (wt) (wt) t su su (d - weh) (d - weh) t h (d) (d) t h (ce) (ce) t rec rec (we) (we) table 4: common memory write timing item symbol ieee symbol min (ns) max (ns) data setup before we t su (d-weh) tdvwh 80 data hold following we t h (d) tlwmdx 30 we pulse width t w (we) twlwh 150 address setup time t su (a) tavwl 30 ce setup before we t su (ce) telwl 0 write recovery time t rec (we) twmax 30 ce hold following we t h (ce) tgheh 20 wait delay falling from we t v (wt-we) twlwtv 35 we high from wait release t v (wt) twthwh 0 wait width time (default speed) t w (wt) twtlwth 350 system ace compactflash solution 8 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r figure 8: ace flash ata memory read timing diagram ds080_10_031301 address address reg reg dout dout ce ce oe oe wait wait t v (wt-oe) (wt-oe) t v (wt) (wt) t su su (a) (a) t su su (ce) (ce) t a (oe) (oe) t w (wt) (wt) t h (ce) (ce) t h (a) (a) t dis dis (oe) (oe) table 5: i/o read timing item symbol ieee symbol min (ns) max (ns) data delay after iord t d (iord) tlglqv 100 data hold following iord t h (iord) tlghqx 0 iord width time t w (iord) tlgligh 165 address setup before iord t su a(iord) tavigl 70 address hold following iord t h a(iord) tlghax 20 ce setup before iord t su ce(iord) teligl 5 ce hold following iord t h ce(iord) tlgheh 20 reg setup before iord t su reg(iord) trgligl 5 reg hold following iord t h reg(iord) tlghrgh 0 inpack delay falling from iord t df inpack(iord) tlglial 0 45 inpack delay rising from iord t dr inpack(iord) tlghiah 45 iois16 delay falling from address t df iois16(adr) tavisl 35 iois16 delay rising from address t dr iois16(adr) tavish 35 wait delay falling from iord t d wt(iord) tlglwtl 35 data delay from wait rising t d (wt) twthqv 0 wait width time (default speed) t w (wt) twtlwth 350 system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 9 advance product specification 1-800-255-7778 r a basic understanding of the typical system ace file and directory structure (shown in figure 9 ) is useful when programming an fpga target system with a compactflash device in the system ace solution. the .ace file is at the lowest level of the directory structure. the xilinx system ace software converts a revision of a design (bitstream) into an .ace file. an .ace file represents a single set of bitstreams for a particular chain of devices. the next level up in the file structure is a collection. the col- lection consists of eight .ace files grouped together. all of the .ace files in a collection (directory) can be addressed when in the system ace environment. there can be sev- eral collections stored on a compactflash device, but only one collection can be active at any given time. the xilinx.sys file determines the collection from which designs can be read. the hierarchical design of the system ace directory struc- ture provides the ability to maintain multiple revisions or col- lections of different designs in a single ace flash device. each collection directory can contain one or more designs that reside in different subdirectories. each design subdi- rectory should contain a single .ace file that represents a single set of bitstreams for a particular chain of devices. in addition to fpga configuration information, the collection and design subdirectories can contain other information pertaining to the system design such as system software, documentation, etc. the xilinx.sys file in the root directory of the ace flash device is used to control which of the designs within the active collection is to be used to configure the chain of tar- get devices. only one collection, containing up to eight designs, can be active at one time. the ace controller parses the xilinx.sys file to determine the active collection designs and uses the three configura- tion address pins or mpu register bits (cfgaddr) to select the desired design. if no xilinx.sys file exists in the root directory of the ace flash device, a single .ace file in the root directory is used by system ace as the active design. following are rules for the system ace directory structure: system ace configuration files must reside on the first partition of the compactflash device. the system ace partition must be formatted as fat12 or fat16. a xilinx.sys or single .ace file must be in the root (project) directory. an .ace file is used only if the xilinx.sys file cannot be found in this directory. only one .ace file should exist in the root and/or design directories. this directory structure allows the configuration controller to be able to use the .ace file to program the fpga target system correctly. figure 9: system ace directory structure ds080_11_032101 dir = rev_3; cfgaddr0 = asia; cfgaddr1 = europe; cfgaddr3 = samerica; cfgaddr4 = diag_1; cfgaddr5 = diag_1; cfgaddr6 = diag_2; cfgaddr7 = diag_2; xilinx.sys project name - (root dir) "/" *.ace *.ace *.ace asia (sub-dir) europe (sub-dir) diag_2 (sub-dir) rev_3 (sub-dir) rev_2 (sub-dir) rev_1 (sub-dir) compactflash available collections collection rev_3 available designs for target fpga chain ace system file containing active collection (up to 8 designs) system ace compactflash solution 10 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r microprocessor interface (mpu) the mpu interface provides a useful means of monitoring the status of and controlling the system ace controller, as well as ace flash card read / write data. the mpu is not required for normal operation, but when used, it pro- vides numerous capabilities. this interface enables commu- nication between an mpu device and a compactflash module and the fpga target system. the mpu interface is composed of a set of registers that provide a means for communicating with compactflash control logic, configuration control logic, and other resources in the ace controller. specifically, this interface can be used to read the identity of a compactflash device and read/write sectors from or to a compactflash device. the mpu interface can also be used to control configuration flow. the mpu interface enables monitoring of ace control- ler configuration status and error conditions. the mpu inter- face can be used to delay configuration, start configuration, determine the source of configuration (compactflash or mpu), control the bitstream version, reset the device, etc. two important issues should be understood when using the microprocessor port: for the controller to be properly synchronized, the mpu must provide the clock. the mpu must comply with system ace timing diagrams. this general-purpose microprocessor interface can update the compactflash, read the ace status or obtain direct access to the jtag configuration ports using the ace microprocessor commands. this interface supports either 8-bit (default) or 16-bit data transfers. the bus width can be configured dynamically. all communications between the ace controller and a host microprocessor involve transfer of data to or from ace reg- isters. there are 128 addressable registers in 8-bit mode and 64 addressable registers in 16-bit mode. for easy selection of a new configuration from compactflash data, the mpu interface allows for easy reconfiguration of an fpga chain or capability. the following sections describe supported operations when using the mpu interface. mpu port signal description mpu interface port signals are described in ta bl e 6 . table 6: mpu interface port signal description name width direction active description mpa 7 in n/a synchronous address inputs. the internal address register is loaded by mpa by a combination of the rising edge of clk and mpce low. mpd 16 in/out n/a synchronous data input/output pins. both the data input and output path are registered and triggered by the rising edge of clk. mpce 1inlow synchronous active low chip enable. mpce low is used to enable the mpu interface. mpce low is also used in conjunction with mpoe low to enable the mpd output. mpwe 1inlow synchronous active low write enable. a high-to-low-to-high transition must occur on mpwe in three consecutive clock cycles in order for the write to take place.during a valid write cycle, mpce must be low and mpd must be valid during the clock cycle that mpwe . mpoe 1inlow asynchronous active low output enable. both mpoe and mpce must be low to read from the mpu interface. when either mpoe or mpce is high, the mpd pins of the ace controller are in a high-impedance state. mpbrdy 1 out high synchronous active high buffer ready output. during data buffer read mode mpbrdy is high when the data in the databuf buffer is valid. during data buffer write mode mpbrdy is high when data can be written to the databuf buffer. mpirq 1 out high synchronous active high interrupt request output. mpirq high indicates that an interrupt condition has occurred in the mpu interface. all interrupt conditions must be manually cleared before mpirq will go low. mpirq is always low when interrupts are disabled. system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 11 advance product specification 1-800-255-7778 r mpu timing description this section contains timing diagrams for the mpu interface. parameters used in the timing diagrams are described in ta b l e 7 . single register read cycle the single register read cycle is shown in figure 10 . a sin- gle register read is accomplished by asserting a valid address (mpa), asserting the chip enable (mpce = low) and de-asserting the write enable (mpwe = high) during the first clock cycle (cycle 0). these signals should hold these values at least until the rising edge of the fourth clock cycle (cycle 3). the output enable signal should be asserted (mpoe = low) during the third clock cycle (cycle 2). register data associated with the specified address appears on the mpd bus two clock cycles after the falling edge of mpce during the assertion of mpce . the register read cycle is then com- pleted by de-asserting the output enable during the fourth clock cycle (cycle 3). table 7: mpu interface timing parameters symbol parameter min max units tsa address setup time 4 -- ns tsce chip enable setup time 4 -- ns tswe write enable setup time 12 -- ns tsoe output enable setup time 12 -- ns tsd data setup time 4 -- ns tdd clock high to valid data -- 22 ns tdoe chip/output enable low to valid data -- 13 ns tdbrdy clock high to buffer ready valid -- 22 ns th hold time 0 -- ns figure 10: single read from an ace register 40ns 60ns 80ns 100ns 120ns 140ns 160 cycle clk mpa mpd mpce mpwe mpoe cycle 0 cycle 1 cycle 2 cycle 3 cycle 4 address data tsa tsce tswe tdd tdoe tdoe tdoe th th th tdoe tsoe th tsoe th tdd ds080_14_013101 system ace compactflash solution 12 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r single register write cycle the single register write cycle is shown in figure 11 . a sin- gle register write is accomplished by asserting a valid address (mpa), asserting the chip enable (mpce = low) and de-asserting the output enable (mpoe = high) during the first clock cycle (cycle 0). these signals should hold these values at least until the rising edge of the third clock cycle (cycle 2). the write enable signal should be asserted (mpwe = low) during the second clock cycle (cycle 1). data (mpd) to be written to the specified address should be asserted during the same clock cycle that the write enable is asserted (cycle 1). the register write cycle is then completed by de-asserting the write enable during the third clock cycle (cycle 2). figure 11: single word write to an ace register 60ns 80ns 100ns 120ns 140ns 160 s cycle clk mpa mpd mpce mpwe mpoe cycle 0 cycle 1 cycle 2 cycle 3 address data tsa tsce th th th th tswe tswe th tsd th tsoe ds080_15_013101 system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 13 advance product specification 1-800-255-7778 r multiple register read timing the minimum timing requirements for sequential register read cycles are shown in figure 12 . sequential read cycles are identical to single read cycles, except that the chip enable (mpce ) and write enable (mpwe ) signals do not need to be de-asserted between read cycles. figure 12: multiple word reads from ace register(s) 50ns 100ns 150ns 200ns 250 0 cycle clk mpa mpd mpce mpwe mpoe cycle 0 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 address <0> address <1> data <0> data <1> tsa tsce tswe tdd tdoe tdoe th th tdoe tsoe th tsoe th th tsa tdoe tdoe th tsoe tdoe th tsoe tdd tdd tdd th ds080_16_013101 system ace compactflash solution 14 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r multiple register write timing the minimum timing requirements for sequential write cycles are shown in figure 13 . sequential write cycles are identical to single write cycles except that the chip enable (mpce ) and output enable (mpoe ) signals do not need to be de-asserted between write cycles. data buffer ready timing the data buffer ready (mpbrdy) signal indicates whether the data buffer is ready to accept new data during a write cycle or whether the data buffer contains valid data to be read during a read cycle. the data buffer itself is sixteen words deep, where each word is 16 bits wide. the data buffer mode transfer direction is identified by the state of the databufmode bit in the statusreg regis- ter: databufmode = 0 indicates data buffer read mode databufmode = 1 indicates data buffer write mode the data buffer mode depends on the type of command that was issued to the ace controller. if an identifymemcard or readmemcard command was issued, then the data buffer remains in read mode until the command is finished execut- ing (i.e., all sector data has been read from the buffer). if a writememcard command was issued, then the data buffer remains in write mode until the command is finished execut- ing (i.e., all sector data has been written to the buffer). figure 13: multiple word writes to ace register(s) 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns 22 cycle clk mpa mpd mpce mpwe mpoe cycle 0 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 address <0> address <1> data <0> data <1> tsa tsce th th th tswe tswe th tsd tsoe tsa th tsd th th th th tswe tswe th ds080_17_020101 system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 15 advance product specification 1-800-255-7778 r data buffer read cycle ready timing when the data buffer is in read mode and the last data word is read from the buffer, the data buffer ready signal will go inactive (mpbrdy = low) two clock cycles following the last clock cycle that the output enable is active (mpoe = low). any attempt to read data out of an ? empty ? data buffer (mpoe = low while mpbrdy = low) results in invalid data. valid and invalid data buffer reads are shown in figure 14 . figure 14: valid and invalid reads from databufreg data buffer 50ns 100ns 150ns 200ns 250 cycle clk mpa mpd mpce mpwe mpoe mpbrdy cycle 0 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 databufreg address databufreg address valid data invalid data tsa tsce tswe tdd tdoe tdoe th th tdoe tsoe th tsoe th th tsa tdoe tdoe th tsoe tdoe th tsoe tdd tdd tdd tdbrdy th ds080_18_020101 system ace compactflash solution 16 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r data buffer read cycle ready timing when the data buffer is in write mode and the last available space for a data word has been filled, the data buffer ready signal will go inactive (mpbrdy = low) two clock cycles following the last clock cycle that the write enable is active (mpwe = low). any attempt to write data to a ? full ? data buffer (mpwe = low while mpbrdy = low) does not result in a successful write to the buffer. valid and invalid data buffer writes are shown in figure 15 . figure 15: valid and invalid writes to databufreg data buffer 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns 22 0 cycle clk mpa mpd mpce mpwe mpoe mpbrdy cycle 0 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 databufreg address databufreg address valid data invalid data tsa tsce th th th tswe tswe th tsd tsoe tsa th tsd th th th th tswe tswe th tbrdy ds080_19_020101 system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 17 advance product specification 1-800-255-7778 r interrupt timing the interrupt request and clearing cycles are shown in figure 16 . in figure 16 , the interrupt request (mpirq = high) occurs sometime before cycle 0. the interrupt request is cleared by performing a single mpu write cycle that sets resetirq = 1 (bit number 11) in the control- reg(15:0) register (byte address 0x19 or word address 0x0c). the mpu interrupt request line (mpirq) remains active high until the resetirq bit is set. the mpirq line becomes inactive low two cycles after the completion of the resetirq write cycle (cycle 4). for subsequent mpu interrupt requests to be enabled, the resetirq bit must be reset and one of the three irq enable bits (databu- frdyirq, errorirq, and/or cfgdoneirq) in the controlreg register should be set. figure 16: interrupt request timing 0ns 50ns 100ns 150ns cycle clk mpa mpd mpce mpwe mpoe mpirq cycle 0 cycle 1 cycle 2 cycle 3 cycle 4 controlreg(15:0) address 0800h tsa tsce th th th th tswe tswe th tsd th tsoe tdirq tdirq ds080_44_030501 system ace compactflash solution 18 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r register specification the byte-mode register space of the mpu interface is shown in ta b l e 8 . table 8: register address map (byte mode addresses) byte address (mpa [6:0]) register name width mode description 0x00 busmodereg 1 rw used to control the data bus access mode (8-bit byte mode or 16-bit word mode) 0x01 busmodereg 1 rw 0x02 -- -- -- reserved 0x03 -- -- -- reserved 0x04 statusreg(7:0) 8 r used to monitor ace controller status 0x05 statusreg(15:8) 8 r 0x06 statusreg(23:16) 8 r 0x07 statusreg(31:24) 8 r 0x08 errorreg(7:0) 8 r used to indicate any existing error condition 0x09 errorreg(15:8) 8 r 0x0a errorreg(23:16) 8 r 0x0b errorreg(31:24) 8 r 0x0c cfglbareg(7:0) 8 r logical block address used by the configuration controller during compactflash data transfers 0x0d cfglbareg(15:8) 8 r 0x0e cfglbareg(23:16) 8 r 0x0f cfglbareg(27:24) 4 r 0x10 mpulbareg(7:0) 8 rw logical block address used by the mpu interface during compactflash data transfers 0x11 mpulbareg(15:8) 8 rw 0x12 mpulbareg(23:16) 8 rw 0x13 mpulbareg(27:24) 4 rw 0x14 seccntcmdreg(7:0) 8 rw sector count and compactflash command register 0x15 seccntcmdreg(15:8) 8 rw 0x16 versionreg(7:0) 8 r version register 0x17 versionreg(15:8) 8 r 0x18 controlreg(7:0) 8 rw used to control ace controller operations 0x19 controlreg(15:8) 8 rw 0x1a controlreg(23:16) 8 rw 0x1b controlreg(31:24) 8 rw 0x1c fatstatreg(7:0) 8 r contains information about the fat table of the first valid partition found in the compactflash device. 0x1d fatstatreg(15:8) 8 r 0x1e through 0x3f -- -- -- reserved even values 0x40 through 0x7e databufreg(7:0) 8 rw address range that provides read and write access to the data buffer. odd values 0x41 through 0x7f databufreg(15:8) 8 rw system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 19 advance product specification 1-800-255-7778 r the 16-bit word mode register space of the mpu interface is shown in ta bl e 9 . table 9: register address map (word mode addresses) word address (mpa [6:1]) register name width mode description 0x00 busmodereg 1 rw used to control the data bus access mode (8-bit byte mode or 16-bit word mode) 0x01 -- -- -- reserved 0x02 statusreg(15:0) 16 r used to monitor ace controller status 0x03 statusreg(31:16) 16 r 0x04 errorreg(15:0) 16 r used to indicate any existing error condition 0x05 errorreg(31:16) 16 r 0x06 cfglbareg(15:0) 16 r logical block address used by the configuration controller during compactflash data transfers 0x07 cfglbareg(27:16) 12 r 0x08 mpulbareg(15:0) 16 rw logical block address used by the mpu interface during compactflash data transfers 0x09 mpulbareg(27:16) 12 rw 0x0a seccntcmdreg(15:0) 16 rw sector count and compactflash command register 0x0b versionreg(15:0) 16 r version register 0x0c controlreg(15:0) 16 rw used to control ace controller operations 0x0d controlreg(31:16) 16 rw 0x0e fatstatreg(15:0) 16 r contains information about the fat table of the first valid partition found in the compactflash device. 0x0f through 0x1f -- -- -- reserved 0x20 through 0x3f databufreg(15:0) 16 rw address range that provides read and write access to the data buffer. system ace compactflash solution 20 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r busmodereg register (byte address 00h-01h, word address 00h) the busmodereg register is used to control the mode of the mpu address and data bus. the single-bit busmodereg register is aliased across two byte addresses (0x00-0x01) and one 16-bit word address (0x0). this register aliasing ensures that the mpu bus mode can be set regardless of the mode of the microprocessor that is communicating with the ace controller. ta b l e 1 0 provides a description of the busmodereg register bits. statusreg register (byte address 04h-07h, word address 02h-03h) the statusreg register allows a microprocessor to monitor important ace controller operating modes. this is also the register that is read upon receiving an irq request in order to identify an interrupt source. ta b l e 1 1 provides a description of the statusreg register bits. table 10: busmodereg register bit descriptions bit name description 0 busmode0 the busmode bits are used to select the width of the data bus portion of the microprocessor/multilinx bus (default is 0): when 0, the mpu interface is in byte mode (all mpu address bits are used, but only mpu data bits 7:0 are used). when 1, the mpu interface is in word mode (all mpu data bits are used, but only mpu address bits 6:1 are used). 1 -- reserved 2 -- reserved 3 -- reserved 4 -- reserved 5 -- reserved 6 -- reserved 7 -- reserved table 11: statusreg register bit descriptions bit name description 0 cfglock configuration controller lock status: 0 means that the configuration controller does not currently have a lock on the compactflash controller resource 1 means that the configuration controller has successfully locked the compactflash controller resource 1 mpulock mpu interface lock status: 0 means that the mpu interface does not currently have a lock on the compactflash controller resource 1 means that the mpu interface has successfully locked the compactflash controller resource 2 cfgerror configuration controller error status: 0 means that no configuration controller error condition exists 1 means that an error has occurred in the configuration controller (check the errorreg register for more information) 3 cfcerror compactflash controller error status: 0 means that no compactflash controller error condition exists 1 means that an error has occurred in the compactflash controller (check the errorreg register for more information) system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 21 advance product specification 1-800-255-7778 r 4 cfdetect compactflash detect flag: 0 means that no compactflash device is connected to the ace controller 1 means that a compactflash is connected to the ace controller 5 databufrdy data buffer ready status: 0 means that the data buffer is not ready for data transfer 1 means that the data buffer is ready for data to be transferred out of the buffer when reading from the compactflash controller or into the buffer when writing to the compactflash or configuration controller 6 databufmode data buffer mode status: 0 means read-only mode 1 means write-only mode 7 cfgdone configuration done status: 0 means that the configuration process has not completed 1 means that the entire ace controller configuration file has been executed and configuration of all devices in the target boundary-scan chain is complete 8 rdyforcfcmd ready for compactflash controller command: 0 means not ready for command 1 means ready for command 9 cfgmodepin configuration mode pin (note that this can be overridden by the cfgmode bit in the controlreg register): 1 means automatically start the configuration process immediately after ace controller reset 0 means wait for cfgstart bit in controlreg before starting the configuration process 10 -- reserved 11 -- reserved 12 -- reserved 13 cfgaddrpin0 configuration address pins that are used as an offset into the system configuration file in the compactflash device used to locate the ace controller configuration data file (note that these pins can be overridden by the contents of the cfgaddrbit[2:0] of the controlreg register) 14 cfgaddrpin1 15 cfgaddrpin2 16 -- reserved 17 cfbsy compactflash busy bit (reflects the state of the bsy bit in the status register of the compactflash device): 0 means that the compactflash device is not busy 1 means that the compactflash command register and data buffer cannot be accessed; bits 1-6 of the statusreg register are not valid when this bit is set 18 cfrdy compactflash ready for operation bit (reflects the state of the rdy bit in the status register of the compactflash device): 0 means the compactflash device is not ready to accept commands 1 means compactflash device is ready to accept commands 19 cfdwf compactflash data write fault bit (reflects the state of the dwf bit in the status register of the compactflash device): 0 means that a write fault has not occurred 1 means that a write fault has occurred table 11: statusreg register bit descriptions (continued) bit name description system ace compactflash solution 22 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r errorreg register (byte address 08h-0bh, word address 04h-05h) the errorreg register identifies specific information on any error conditions that might exist in the ace controller. ta b l e 1 2 provides a description of the errorreg register bits. 20 cfdsc compactflash ready bit (reflects the state of the dsc bit in the status register of the compactflash device): 0 means that the compactflash device is not ready 1 means that the compactflash device is ready 21 cfdrq compactflash data request bit (reflects the state of the drq bit in the status register of the compactflash device): 0 means that no data is ready to be transferred to/from the data buffer of the compactflash device 1 means that information be transferred to/from the data buffer of the compactflash device 22 cfcorr compactflash correctable error bit (reflects the state of the corr bit in the status register of the compactflash device): 0 means that a correctable data error was not encountered 1 means that a correctable data error was encountered (check the errorreg register for more information) 23 cferr compactflash error bit (reflects the state of the err bit in the status register of the compactflash device): 0 means that no error has occurred during the execution of the previous command 1 means that the previous command has ended in some type of error (check the errorreg register for more information) 24 -- reserved 25 -- reserved 26 -- reserved 27 -- reserved 28 -- reserved 29 -- reserved 30 -- reserved 31 -- reserved table 12: errorreg register bit descriptions bit name description 0 cardreseterr compactflash card reset error: 0 means no error 1 means that the compactflash card has failed to reset properly before a time-out condition occurred 1 cardrdyerr compactflash card ready error: 0 means no error 1 means that the compactflash card has failed to become properly ready for commands before a time-out condition occurred 2 cardreaderr compactflash card read error: 0 means no error 1 means that a compactflash data read command (either readmemcarddata or identifymemcard) has failed table 11: statusreg register bit descriptions (continued) bit name description system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 23 advance product specification 1-800-255-7778 r 3 cardwriteerr compactflash card write error: 0 means no error 1 means that a compactflash data write command (writememcarddata) has failed 4 sectorrdyerr compactflash sector ready: 0 means no error 1 means that a sector has failed to become properly valid during a compactflash read or write command before a time-out condition occurred 5 cfgaddrerr cfgaddr error: 0 means no error 1 means that the cfgaddr (i.e., the cfgaddr(15:0) register or cfgaddr(1:0) pins, depending on the state of the forcecfgaddr bit in the controlreg register) does not correspond to a valid location in the compactflash 6 cfgfailed configuration failure error: 0 means no error 1 means that configuration of one or more devices in the target boundary-scan chain has failed 7 cfgreaderr configuration read error: 0 means no error 1 means that an error occurred while reading configuration information from compactflash 8 cfginstrerr configuration instruction error: 0 means no error 1 means that an invalid instruction was encountered during configuration 9 cfginiterr configuration init monitor error: 0 means no error 1 means that the cfginit pin did not go high within 500 ms of the start of configuration 10 -- reserved 11 cfbbk compactflash bad block error (reflects the state of the bbk bit in the error register of the compactflash device): 0 means no error 1 means that a bad block has been detected 12 cfunc compactflash uncorrectable error (reflects the state of the unc bit in the error register of the compactflash device): 0 means no error 1 means that an uncorrectable error has been encountered 13 cfidnf compactflash id not found error (reflects the state of the idnf bit in the error register of the compactflash device): 0 means no error 1 means that the requested sector id is in error or cannot be found 14 cfabort compactflash command abort error (reflects the state of the abrt bit in the error register of the compactflash device): 0 means no error 1 means that the command has been aborted because of a compactflash status condition (i.e., not ready, write fault) or when an invalid command has been issued table 12: errorreg register bit descriptions (continued) bit name description system ace compactflash solution 24 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r 15 cfamnf compactflash general error (reflects the state of the amnf bit in the error register of the compactflash device): 0 means no error 1 means that a general error has occurred 16 -- reserved 17 -- reserved 18 -- reserved 19 -- reserved 20 -- reserved 21 -- reserved 22 -- reserved 23 -- reserved 24 -- reserved 25 -- reserved 26 -- reserved 27 -- reserved 28 -- reserved 29 -- reserved 30 -- reserved 31 -- reserved table 12: errorreg register bit descriptions (continued) bit name description system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 25 advance product specification 1-800-255-7778 r cfglbareg register (byte address 0ch-0fh, word address 06h-07h) the cfglbareg read-only register contains the logical block address used by the ace controller configuration logic during compactflash read/write operations. the cfglbareg register affects only transfers between the ace controller configuration logic and the compactflash card. the mpu uses a separate set of registers (mpulbareg(27:0)) to transfer data to and from the compactflash card. ta b l e 1 3 provides a description of the cfglbareg register bits. table 13: cfglbareg register bit descriptions bit name description 0 cfglba00 logical block address used during compactflash read or write sector commands: each block address points to a sector location which is made up of 512 bytes (i.e., maximum compactflash device capacity is up to 128 gigabytes, or 137,438,953,472 bytes) 1cfglba01 2cfglba02 3cfglba03 4cfglba04 5cfglba05 6cfglba06 7cfglba07 8cfglba08 9cfglba09 10 cfglba10 11 cfglba11 12 cfglba12 13 cfglba13 14 cfglba14 15 cfglba15 16 cfglba16 17 cfglba17 18 cfglba18 19 cfglba19 20 cfglba20 21 cfglba21 22 cfglba22 23 cfglba23 24 cfglba24 25 cfglba25 26 cfglba26 27 cfglba27 28 -- reserved 29 -- reserved 30 -- reserved 31 -- reserved system ace compactflash solution 26 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r mpulbareg register (byte address 10h-13h, word address 08h-09h) the mpulbareg read-write register contains the logical block address that is used by the mpu interface during compactflash read/write operations. the mpulbareg register affects only transfers between the mpu interface and the compactflash card. ace controller configuration logic maintains a separate set of registers (cfglbareg(27:0)) for use when transferring data to and from the compactflash card. ta b l e 1 4 provides a description of mpulbareg register bits. table 14: mpulbareg register bit descriptions bit name description 0 mpulba00 logical block address used during compactflash read or write sector commands: each block address points to a sector location which is made up of 512 bytes (i.e., maximum compactflash device capacity is up to 128 gigabytes, or 137,438,953,472 bytes) 1mpulba01 2mpulba02 3mpulba03 4mpulba04 5mpulba05 6mpulba06 7mpulba07 8mpulba08 9mpulba09 10 mpulba10 11 mpulba11 12 mpulba12 13 mpulba13 14 mpulba14 15 mpulba15 16 mpulba16 17 mpulba17 18 mpulba18 19 mpulba19 20 mpulba20 21 mpulba21 22 mpulba22 23 mpulba23 24 mpulba24 25 mpulba25 26 mpulba26 27 mpulba27 28 -- reserved 29 -- reserved 30 -- reserved 31 -- reserved system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 27 advance product specification 1-800-255-7778 r seccntcmdreg register (byte address 014h-15h, word address 0ah) the seccntcmdreg register provides the means for an mpu interface to set the sector count and execute com- pactflash controller commands. ta b l e 1 5 provides a description of the seccntcmdreg register bits. the seccnt bits of the seccntcmdreg register spec- ify the number of sectors to transfer during each readmem- carddata or writememcarddata command: a seccnt value of 1 to 255 indicates to the compactflash device that 1 to 255 sectors should be transferred. a seccnt value of 0 indicates that 256 sectors should be transferred. the cmd bits of the seccntcmdreg register identify a specific command to be executed: if the mpu has not successfully locked access to the compactflash controller, then writes to the cmd bits of the seccntcmdreg register do not change the value of the register. if the mpu has successfully locked access to the compactflash controller and a non-zero value is written to the cmd bits of the seccntcmdreg register, then the specified command is executed by the compactflash controller. if the mpu has successfully locked access to the compactflash controller and a zero value is written to the cmd bits of the seccntcmdreg register, there is no effect on the value of the cmd bits. the only way to clear the cmd bits is to issue the cfabort command, which aborts the currently executing command and waits until the compactflash controller clears the cmd bits. table 15: seccntcmdreg register bit descriptions bit name description 0 seccnt0 sector count used during compactflash read or write sector commands: each sector is made up of 512 bytes 1 seccnt1 2 seccnt2 3 seccnt3 4 seccnt4 5 seccnt5 6 seccnt6 7 seccnt7 8 cmd0 command value: 0x0 : reserved 0x1 : resetmemcard command 0x2 : identifymemcard command 0x3 : readmemcarddata command 0x4 : writememcarddata command 0x5: reserved 0x6 : abort command 0x7 : reserved 9cmd1 10 cmd2 11 -- reserved 12 -- reserved 13 -- reserved 14 -- reserved 15 -- reserved system ace compactflash solution 28 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r versionreg register (byte address 16h-17h, word address 0bh) the versionreg register holds the ace controller version number in the form of a 4-bit major version field, a 4-bit minor version field, and an 8-bit revision/build number field. ta b l e 1 6 provides a description of the versionreg register bits. table 16: versionreg register bit descriptions bit name description 0 version0 revision / build number: msb is bit 7, lsb is bit 0 1 version1 2 version2 3 version3 4 version4 5 version5 6 version6 7 version7 8 version8 minor version number: msb is bit 11, lsb is bit 8 9 version9 10 version10 11 version11 12 version12 major version number: msb is bit 15, lsb is bit 12 13 version13 14 version14 15 version15 system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 29 advance product specification 1-800-255-7778 r controlreg register (byte address 18h-1bh, word address 0ch-0dh) the controlreg register provides the means for the mpu interface to control ace controller functionality. ta b l e 1 7 provides a description of the controlreg register bits. table 17: controlreg register bit descriptions bit name description 0 forcelockreq forces the compactflash arbitration logic to grant a lock to the mpu interface based on the value of the lockreq bit of the controlreg register (default is 0): 0 means do not force mpu lock request (i.e., arbitrate between configuration controller and mpu interface) 1 means force mpu lock request (i.e., do not perform arbitration: grant lock request based only on mpu requests) 1 lockreq cf arbitration lock request signal; once a lock is granted, the lockreq must be de-asserted before the lock is removed (default is 0): 0 means do not request compactflash access lock 1 means request compactflash access lock 2 forcecfgaddr forces the overriding of the cfgaddr(1:0) pins in favor of using the cfgaddrbit(2:0) bits of the controlreg(15:13) register (default is 0): 0 means use the cfgaddr(1:0) pins 1 means use the controlreg(15:13) register bits 3 forcecfgmode forces the overriding of cfgmodepin in favor of using the cfgmode bit of the controlreg register (default is 0): 0 means use cfgmodepin 1 means use the cfgmode bit of the controlreg register 4 cfgmode configuration mode (default is 0): 1 means automatically start the configuration process immediately after ace controller reset 0 means wait for cfgstart bit in controlreg before starting the configuration process 5 cfgstart configuration start bit (default is 0): 0 means do not start configuration 1 means start configuration process 6 cfgsel configuration select (default is 0): 0 means configure from compactflash 1 means configure from mpu interface 7 cfgreset configuration/compactflash controller reset (default is 0): 0 means do not reset 1 means reset the configuration and compactflash controllers (this also causes a ? soft-reset ? of the compactflash device) 8 databufrdyirq data buffer ready irq enable (default is 0): 1 means interrupts are enabled for when data buffer is ready for transfer of data into or out of the buffer 0 means data buffer ready interrupts are disabled 9 errorirq error irq enable (default is 0): 1 means interrupts are enabled for when an error occurs 0 means error interrupts are disabled system ace compactflash solution 30 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r 10 cfgdoneirq configuration done irq enable (default is 0): 1 means interrupts are enabled for when configuration is done 0 means configuration done interrupts are disabled 11 resetirq resets the interrupt request line when a ? 1 ? is written to this register bit. note that a ? 0 ? must be written to this register bit in order to re-arm for subsequent interrupt conditions. 12 cfgprog inverted ace controller cfgprog pin control (default is 0): 0 means set the cfgprog pin to its inactive high state of 1 1 means set the cfgprog pin to its active low state of 0 13 cfgaddrbit0 configuration address register bits that are used as an offset into the system configuration file in the compactflash device used to locate the ace controller configuration data file (note that these register bits can be used to override the cfgaddr[2:0] pins of the ace controller) 14 cfgaddrbit1 15 cfgaddrbit2 16 cfgrsvd0 reserved for future use. these bits must be set to zero at all times. 17 cfgrsvd1 18 cfgrsvd2 19 -- reserved 20 -- reserved 21 -- reserved 22 -- reserved 23 -- reserved 24 -- reserved 25 -- reserved 26 -- reserved 27 -- reserved 28 -- reserved 29 -- reserved 30 -- reserved 31 -- reserved table 17: controlreg register bit descriptions (continued) bit name description system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 31 advance product specification 1-800-255-7778 r fatstatreg register (byte address 1ch-1dh, word address 0eh) the fatstatreg register contains information about the first valid partition of the compactflash device such as the boot record and fat types found. ta bl e 1 8 provides a description of the fatstatreg register bits. table 18: fatstatreg register bit descriptions bit name description 0 mbrvalid master boot record (mbr) valid flag: 0 means no mbr was detected 1 means a valid mbr was found 1 pbrvalid partition boot record (pbr) valid flag: 0 means no pbr was detected 1 means a valid pbr was found 2 mbrfat12 master boot record (mbr) fat12 flag: 0 means fat12 flag is not set in mbr 1 means fat12 flag is set in mbr 3 pbrfat12 partition boot record (pbr) fat12 flag: 0 means fat12 flag is not set in pbr 1 means fat12 flag is set in pbr 4 mbrfat16 master boot record (mbr) fat16 flag: 0 means fat16 flag is not set in mbr 1 means fat16 flag is set in mbr 5 pbrfat16 partition boot record (pbr) fat16 flag: 0 means fat16 flag is not set in pbr 1 means fat16 flag is set in pbr 6 calcfat12 calculated fat12 flag (based on cluster count): 0 means not fat12 (cluster count > 4085) 1 means fat12 (cluster count < 4085) 7 calcfat16 calculated fat12 flag (based on cluster count): 0 means not fat16 (cluster count > 65525) 1 means fat16 (4085 < cluster count < 65535) 8 -- reserved 9 -- reserved 10 -- reserved 11 -- reserved 12 -- reserved 13 -- reserved 14 -- reserved 15 -- reserved system ace compactflash solution 32 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r databufreg register (byte address 40h-7fh, word address 20h-3fh) the databufreg register is the portal register to the data buffer that is used to transfer data between the mpu interface and the compactflash and/or configuration controllers. the description of the databufreg register bits are shown in ta b l e 1 9 . test jtag interface (tstjtag) the test jtag interface (tstjtag) supports 1149.1 boundary-scan operations on the ace controller and all chained fpga devices connected to the configuration jtag (cfgjtag) port. this interface can also be used to program the target fpga chain on the cfgjtag port, using xilinx or third-party jtag programming tools. the ace controller is fully compliant with the ieee 1149.1 boundary-scan standard, commonly referred to as jtag. as shown in figure 17 , a test access port (tap), instruction decoder, and the required ieee 1149.1 registers are included in the ace controller to support the mandatory boundary-scan instructions. in addition, the controller also supports an optional 32-bit identification register. refer to the 1149.1 boundary-scan standard specification for a complete description of the required instructions and detailed information on jtag. table 19: databufreg register bit descriptions bit name description 0 data00 data buffer portal register: data register bits are read-only when the databufmode bit in the statusreg register is a 0, otherwise they are write-only when the databufmode bit is a 1. databufreg(07:00) are accessible in byte and word bus modes. 1data01 2data02 3data03 4data04 5data05 6data06 7data07 8 data08 data register: data register bits are read-only when the databufmode bit in the statusreg register is a 0, otherwise they are write-only when the databufmode bit is a 1. databufreg(15:08) are accessible in byte and word bus modes. during byte bus write mode, if the data buffer is ready, any writes to the databufreg(15:08) bits cause the databufreg(15:00) contents to be written to the data buffer. during byte bus read mode, if the data buffer is ready, the databufreg(15:00) register will hold the current value until the databufreg(15:08) bits are read. after databufreg(15:08) is read, the databufreg(15:00) register is loaded with any pending new data. 9data09 10 data10 11 data11 12 data12 13 data13 14 data14 15 data15 table 20: ace controller tap pins pins description tsttdi (tdi) test data in tsttdo (tdo) test data out tsttms (tms) test mode select tsttck (tck) test clock system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 33 advance product specification 1-800-255-7778 r the tstjtag logic is connected to the cfgjtag port as long as the compactflash and mpu interfaces are not connected to the cfgjtag port. outlined in the following sections are the details of the jtag interface for the ace controller. the available boundary-scan registers for the ace controller are shown in ta b l e 2 1 . instruction register the instruction register (ir) for the ace controller is eight bits wide and is connected between tdi and tdo during an instruction scan sequence. the instruction register is parallel loaded with a fixed instruction capture pattern in preparation for an instruction sequence. this pattern is shifted out onto tdo (lsb first), while an instruction is shifted into the instruc tion register from tdi. this pattern is illustrated in ta b l e 2 2 . the optional idcode instruction is supported in addition to the mandatory instructions (bypass, sample/preload, and extest). the binary values for these instructions are listed in ta b l e 2 3 . figure 17: test jtag interface block diagram tap controller logic identifcation register instruction register bypass register boundary scan register 1 0 tsttdi tsttms tsttck cfgtdo tsttdo cfgtck cfgtms cfgtdi cfgsel (from core) cfgdata (from core) ds080_45_030801 table 21: ace controller boundary-scan registers register name register length description instruction register 8 bits holds current instruction opcode and captures internal device status. boundary-scan register 109 bits controls and observes input, output, and output enable. identification register 32 bits captures device idcode. bypass register 1 bit device bypass. table 22: instruction register values loaded into ir during instruction scan sequence ir[7] ir[6] ir[5] ir[4] ir[3] ir[2] ir[1: 0] cfginstrerr (mpu errorreg register bit) cfgfailed (mpu errorreg register bit) cfgreaderr (mpu errorreg register bit) cfcerror (mpu statusreg register bit) cfgerror (mpu statusreg register bit) cfgdone 01 system ace compactflash solution 34 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r boundary-scan register the boundary-scan register, which is the primary test data register, is used to control and observe the state of device pins during extest and sample/preload instructions. for more information on the system ace boundary-scan register (such as bit sequence, 3-state control, and so forth), refer to the system ace boundary-scan description language (bsdl) file available from the software download area at: www.xilinx.com . bit sequence the bit sequence of the device is obtainable from the boundary-scan description language (bsdl) files. these files are available from the software download area at: www.xilinx.com . identification register the identification register known as the idcode is a fixed, vendor-assigned value that is used to electronically identify the type of device and the manufacturer for a specific device being tested. the ace controller idcode register is 32 bits wide. the contents of this register can be shifted out for examination by selecting the idcode instruction. the idcode is available to any other system component via jtag. the idcode register has the following binary format, described in ta b l e 2 4 : vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 bypass register the last standard 1149.1 boundary-scan data register in the ace controller is the single flip-flop bypass register. it directly passes data serially from the tdi pin to the tdo pin during a bypass instruction. this register is initialized to zero when the tap controller is in the update-dr state. tap timing characteristics ieee 1149.1 boundary-scan (jtag) testing is performed via the standard 4-wire test access port (tap). the boundary scan timing waveforms and switching characteristics of the tap are described in figure 18 and ta b l e 2 5 , respectively. table 23: ace controller boundary-scan instructions boundary-scan instruction binary code [7:0] description bypass 11111111 enables bypass sample/preload 00000001 enables boundary-scan sample/preload operation idcode 00001001 enables shifting out 32-bit idcode extest 00000000 enables boundary-scan extest operation table 24: ace controller identification register version family array size manufacturer required by 1149.1 0000 0000001 00000000 00001001001 1 figure 18: test jtag boundary-scan port timing waveforms 0ns 50ns 100ns 150ns 2 tsttms tsttdi tsttck tsttdo valid ttcktdo ttaptck ttaptck ttcktap ttcktap ds080_46_030801 system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 35 advance product specification 1-800-255-7778 r configuration jtag interface (cfgjtag) configuration jtag port is the interface between the ace controller and the target fpga chain. this port is accessed when configuring the target fpga chain of devices via any of the ace controller interfaces (test jtag, mpu, or compactflash). to program or test the fpga target chain, the data from these interfaces is converted to 1149.1 boundary-scan (jtag) serial data. typical configuration modes the four ace controller interfaces are designed to work together in a number of different combinations. this section discusses typical user configuration modes. a handful of signals determine which interface provides the configuration data source. ta b l e 2 6 describes these important signals, and ta bl e 2 7 shows how they work together to determine which interface will be used. this is especially important when using multiple interfaces in a design, or when not using the default values of these signals. the default values of these signals set the compactflash interface as the source of configuration data. table 25: system ace controller tap characteristics symbol parameter min max units t (taptck) tsttms and tsttdi setup time before rising edge of tsttck 4 ns t (tcktap) tsttms and tsttdi hold times after tsttck 0 ns t (tcktdo) tsttck falling edges to tsttdo output valid 16 ns f (tsttck) maximum tsttck clock frequency 16.7 mhz table 26: configuration signals used for selecting configuration modes and active design configuration signal description default cfgmode pin or mpu register bit cfgmodepin = 1 cfgmode register bit = 0 cfgaddr[2:0] pins or mpu register bits 0 cfgsel mpu register bit 0 cfgstart mpu register bit 0 cfgreset mpu register bit (cfgreset is a subset of the reset pin) 0 forcecfgaddr mpu register bit (overrides value on cfgaddr [2:0] pins) 0 forcecfgmode mpu register bit (overrides value on cfgmodepin) 0 table 27: active configuration modes configuration interface cfgmode (1) cfgsel cfgstart cfgreset compactflash (configure from cf immediately after reset) 10x (2) 0 compactflash (configure from cf after receiving mpu start signal) 001 0 microprocessor (configure from mpu after receiving mpu start signal) 111 0 microprocessor (configure from mpu) 11x 0 test jtag (configure using the tstjtag port) 1x 0 0 notes: 2. the forcecfgmode bit in the controlreg register of the mpu interface can be used to force the cfgmode register bit to override the ace controller cfgmodepin. 3. an x entry indicates ? don ? t care ? . system ace compactflash solution 36 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r compactflash (cf) to configuration jtag (cfgjtag) setup this setup provides a standard compactflash interface for high-density fpga systems. the compactflash interface is the source of configuration data. the data configures the xilinx fpga chain through boundary-scan (jtag) using the configuration jtag port, as shown in figure 19 . the ace controller handles all necessary steps to perform configuration from the cf to the target system. the appropriate signal connections for this setup are shown in figure 20 . this setup can be used in conjunction with any of the other interfaces. figure 19: data flow diagram of cf to cfgjtag mpu tsttdi ta p ctrl. compactflash ace controller core tsttdo tdo tdi cfgtdo cfgtdi tdi tdo tdi tdo tdo tdi ds080_22_030801 *cfcgtck and cfgtms lines are driven by ace controller core logic and are broadcast to all target devices. bs n a c (test jtag port) (configuration jtag port) system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 37 advance product specification 1-800-255-7778 r compactflash (cf) to microprocessor (mpu) setup this setup provides a standard compactflash to mpu interface for high-density fpga systems. this interface provides a great deal of flexibility. the ability to communicate with the cf through the mpu port allows the user to perform many operations, such as being able to switch the programming .ace file so that it can be used for the target system. figure 20: wiring diagram for cf to cfgjtag ace controller compactflash device cfd(15:0) cfa(10:0) d(15:0) a(10:0) xilinx fpga target chain cfgtms tms cfgtck cfgtdi cfgtdo tck tdo tdi ds080_24_121201 ce1 ce2 we oe wait reg cd1 cd2 cfce1 cfce2 cfwe cfoe cfwait cfreg cfcd1 cfcd2 cfgprog cfginit program init statled reset errled v cc v cc 5.1 k ? 5.1 k ? 1.0 k ? 1.0 k ? reset v cc v cc 180 ? 180 ? 5.1 k ? cfrsvd v cc cfreset csel iowr iord figure 21: data flow diagram of cf to mpu ta p ctrl. tdo tdi cfgtdo cfgtdi tdi tdo tdi tdo tdo tdi ds080_28_030801 bs n a c mpu compactflash ace controller core tsttdi tsttdo (test jtag port) (configuration jtag port) system ace compactflash solution 38 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r the ace controller handles all necessary steps to perform a cf to mpu operation. this setup uses the cf to mpu signals shown in the wiring diagram in figure 22 . figure 22: wiring diagram cf to mpu ace controller mpu device clk mpbrdy mpirq mpa(6:0) mpd(15:0) ds080_27_121201 compactflash device d(15:0) a(10:0) cfd(15:0) cfa(10:0) refer to the microprocessor or microcontroller data sheet for appropriate signal names. ce2 ce1 we oe wait reg cd1 cd2 cfce1 cfce2 cfwe cfoe cfwait cfreg cfcd1 cfcd2 reset statled errled mpce mpwe mpoe v cc v cc 5.1 k ? 5.1 k ? 1.0 k ? 1.0 k ? iowr iord csel cfreset v cc v cc 5.1 k ? cfrsvd v cc 180 ? 180 ? system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 39 advance product specification 1-800-255-7778 r reading sector data from compact flash control flow process sector data can be read from the compactflash device via the mpu interface of the systemace controller by following the control flow sequence shown in figure 23 . the first step in the sequence of accessing the compactflash interface is to arbitrate for a lock. the control flow process for obtaining a compactflash resource lock is shown in figure 24 . once the mpu interface has been granted a compactflash lock, the mpu interface needs to make sure that the compact- flash device is ready to receive a command. the process for polling the command readiness indicator is shown in figure 25 . figure 23: reading sector data from compactflash control flow process set readmemcarddata command control set mpu lba set sector count control initialize buffer count variable* read data buffer release cf lock data is read. return success. buffer count equal to 0? decrement buffer count variable no yes *set buffer count variable equal to the number of buffers in a sector transfer = ((sector count)*(512 bytes per sector))/ (32 bytes per buffer) = (sector count) * (16 buffers per sector) read data from cf get cf lock check if ready for command ? write lba bits 7:0 to byte address 10h write lba bits 15:8 to byte address 11h write lba bits 23:16 to byte address 12h write lba bits 27:24 to byte address 13h write seccnt bits 7:0 to byte address 14h w rite cfgreset bit = 1 to byte address 18h w rite lockreq bit = 0 to byte address 18h reset configuration controller clear configuration controller reset w rite cfgreset bit = 0 to byte address 18h write cmd bits to byte address 15h ds080_48_051701 system ace compactflash solution 40 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r once the compactflash device is ready to receive a new command, the following information needs to be written to the mpu interface: 1. the sector address or logical block address (lba) of the first sector to be transferred should be written to the following mpu address locations: - lba[7:0] @ mpu byte address 10h - lba[15:8] @ mpu byte address 11h - lba[23:16] @ mpu byte address 12h - lba[27:24] @ mpu byte address 13h (note that only four bits are used in the most significant lba byte) 2. the number of sectors to be read should be written to the low byte of the seccntcmdreg register (mpu byte address 14h) 3. the readmemcarddata command (03h) should be written to the high byte of the seccntcmdreg register (mpu byte address 15h) 4. reset the cfgjtag controller by setting the cfgreset bit (bit 7) of the controlreg register (mpu address 18h) to a 1. immediately after writing the command to the mpu inter- face, the cfgjtag controller should be reset before read- ing the sector data from the data buffer. the control flow process for reading the sector data from the data buffer is shown in figure 26 . after all of the requested sector data has been read, the cfgjtag controller should be taken out of reset and the compactflash lock should be released by setting the lockreq bit (bit 1) and cfgreset bit (bit 7) of the low byte of the controlreg register (mpu byte address 18h) to a 0. note that all requested sector data should be read from the data buffer in order to avoid a deadlock situa- tion with the compactflash device. system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 41 advance product specification 1-800-255-7778 r get compactflash lock control flow process the compactflash resource must be arbitrated for before it can be accessed via the mpu interface. the compactflash arbitration process is shown in figure 24 . a compactflash lock is requested by setting the lockreq bit (bit 1) to a 1 in the controlreg register (mpu address 18h) and poll- ing the mpulock bit (bit 1) in the statusreg register (mpu byte address 04h). note that if the cfglock bit (bit 0) in the statusreg reg- ister (mpu byte address 04h) is set, then the cfgjtag controller has locked the compactflash resource. in this case, the mpu interface must either wait for the cfgjtag interface to release the lock or it can force the lock to be released. this is done by resetting the cfgjtag controller by setting the cfgreset bit (bit 7) and the forcelock- req bit (bit 0) in the controlreg register (mpu byte address 18h). the lock request process can be started again after forcing the cfgjtag controller to release the lock. figure 24: get compactflash lock control flow process cf locked? timer expired? decrement timer variable cf is busy. return timeout error. cf is locked. return success. no yes no yes write lockreq bit = 1 to byte address 18h get cf lock set lock control initialize timer variable get lock status read mpulock bit from byte address 04h ds080_49_051701 system ace compactflash solution 42 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r check if ready for a command control flow process before reading or writing sector data, it is important to make sure that the compactflash device is ready for a command. this is done by polling the rdyforcfcmd bit (bit 0) in the second byte of the statusreg register (mpu byte address 05h) until it is set to a 1. this control flow process is shown in figure 25 . figure 25: check if ready for a command control flow process check if ready for command get command ready status ready for command? timer expired? decrement timer variable initialize timer variable busy. return timeout error. ready. return success. no yes no yes read rdyforcmd bit from byte address 05h ds080_50_051701 system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 43 advance product specification 1-800-255-7778 r read data buffer control flow process the control flow process for reading from the data buffer is shown in figure 26 . the systemace data buffer is imple- mented as a 32-byte (16-word) deep fifo that is aliased across a range of mpu byte addresses (40h through 7fh) in order to facilitate burst transfers across the mpu interface. sector data is read from the data buffer by first waiting for the buffer to become ready (i.e., full of sector data), as shown in figure 27 . once the buffer is ready, then all 32 bytes can be read from the buffer from alternating even and odd byte addresses. reading from an odd byte address while in byte mode causes the fifo to increment the data word to the next available word in the fifo. reading from any data buffer address while in word mode will cause the fifo to increment. figure 26: read data buffer control flow process read data word from buffer decrement data count variable data count equal to 0? buffer is written. return success. yes no wait for buffer ready read data buffer initialize data count variable* *set data count variable equal to the number of data items in a buffer (e.g., 16 bytes or 32 words) read data bits 7:0 from byte address 40h read data bits 15:8 from byte address 41h (note that the following conditions must be valid for a data read to occur from the compactflash data buffer: 1. the data buffer must be ready 2. a single read from byte address 41h must occur that will cause the entire 16- bit data register to be overwritten by the buffer with new data) ds080_51_051701 system ace compactflash solution 44 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r wait for buffer ready control flow process the readiness of the systemace data buffer indicates that the buffer is either full during a readmemcarddata com- mand execution or empty during a writememcarddata command execution. the control flow process for waiting for the buffer to become ready is shown in figure 27 . the buffer ready status can be obtained from either the databufrdy bit (bit 5) of the statusreg register (mpu byte address 04h) or from the mpbrdy pin of the sys- temace controller. figure 27: wait for buffer ready control flow process wait for buffer ready get buffer ready status buffer ready? timer expired? decrement timer variable initialize timer variable buffer not ready. return timeout error. buffer is ready. return success. no yes no yes read databufrdy bit from byte address 04h ds080_52_051701 system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 45 advance product specification 1-800-255-7778 r microprocessor (mpu) to compactflash (cf) setup this setup provides a communication path from the mpu to the cf device. the compactflash is the source of the configuration data, and this path enables users to read the contents of the cf device. the ace controller handles all necessary steps to perform an mpu to cf operation. the necessary signals for this setup are shown in figure 22 . figure 28: data flow diagram of mpu to cf mpu tsttdi ta p ctrl. compactflash tsttdo tdo tdi cfgtdo cfgtdi tdi tdo tdi tdo tdo tdi ds080_25_030801 bs n a c ace controller core (test jtag port) (configuration jtag port) system ace compactflash solution 46 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r writing sector data to compact flash control flow process sector data can be written to the compactflash device via the mpu interface of the systemace controller by following the control flow sequence shown in figure 29 . the first step in the sequence of accessing the compactflash interface is to arbitrate for a lock. the control flow process for obtaining a compactflash resource lock is shown in figure 24 . once the mpu interface has been granted a compactflash lock, the mpu interface needs to make sure that the compact- flash device is ready to receive a command. the process for polling the command readiness indicator is shown in figure 25 . figure 29: write data to compactflash control flow process set mpu lba set writememcarddata command control set sector count control initialize buffer count variable* write data buffer release cf lock data is written. return success. buffer count equal to 0? decrement buffer count variable no yes *set buffer count variable equal to the number of buffers in a sector transfer = ((sector count)*(512 bytes per sector))/ (32 bytes per buffer) = (sector count) * (16 buffers per sector) write data to cf get cf lock check if ready for command write lba bits 7:0 to byte address 10h write lba bits 15:8 to byte address 11h write lba bits 23:16 to byte address 12h write lba bits 27:24 to byte address 13h write seccnt bits 7:0 to byte address 14h write cfgreset bit = 1 to byte address 18h write lockreq bit = 0 to byte address 18h reset configuration controller clear configuration controller reset write cfgreset bit = 0 to byte address 18h write cmd bits to byte address 15h ds080_053_051701 system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 47 advance product specification 1-800-255-7778 r once the compactflash device is ready to receive a new command, the following information needs to be written to the mpu interface: 1. the sector address or logical block address (lba) of the first sector to be transferred should be written to the following mpu address locations: - lba[7:0] @ mpu byte address 10h - lba[15:8] @ mpu byte address 11h - lba[23:16] @ mpu byte address 12h - lba[27:24] @ mpu byte address 13h (note that only four bits are used in the most significant lba byte) 2. the number of sectors that will be written should be loaded into the low byte of the seccntcmdreg register (mpu byte address 14h) 3. the writememcarddata command (04h) should be written to the high byte of the seccntcmdreg register (mpu byte address 15h) 4. reset the cfgjtag controller by setting the cfgreset bit (bit 7) of the controlreg register (mpu address 18h) to a 1. immediately after writing the command to the mpu inter- face, the cfgjtag controller should be reset before writing the sector data to the data buffer. the control flow process for writing the sector data from the data buffer is shown in figure 30 . after all of the required sector data has been written, the cfgjtag controller should be taken out of reset and the compactflash lock should be released. this is done by set- ting the cfgreset (bit 7) and lockreq (bit 1) bits of the low byte of the controlreg register (mpu byte address 18h) to a 0, respectively. note that all requested sector data should be written to the data buffer in order to avoid a dead- lock situation with the compactflash device. figure 30: write data buffer control flow process write data word to buffer decrement data count variable data count equal to 0? buffer is written. return success. yes no wait for buffer ready write data buffer initialize data count variable* *set data count variable equal to the number of data items in a buffer (e.g., 16 bytes or 32 words) write data bits 7:0 to byte address 40h write data bits 15:8 to byte address 41h (note that the following conditions must be valid for a data write to occur to the compactflash data buffer: 1. the data buffer must be ready 2. a single write to byte address 41h must occur that will cause the entire 16- bit data register to be written to the buffer) ds080_54_051701 system ace compactflash solution 48 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r write data buffer control flow process the control flow process for writing to the data buffer is shown in figure 30 . the systemace data buffer is imple- mented as a 32-byte (16-word) deep fifo that is aliased across a range of mpu byte addresses (40h through 7fh) in order to facilitate burst transfers across the mpu interface. sector data is written to the data buffer by first waiting for the buffer to become ready (i.e., empty of any sector data), as shown in figure 27 . once the buffer is ready, then all 32 bytes can be written to the buffer to alternating even and odd byte addresses. writing to an odd byte address while in byte mode causes the fifo to increment the data word to the next available word in the fifo. writing to any data buffer address while in word mode will cause the fifo to increment. microprocessor (mpu) to configuration jtag (cfgjtag) setup this setup provides an mpu to cfgjtag communication path. the data configures the fpga system through jtag via the configuration jtag port. the ace controller handles all necessary steps to perform configuration using the mpu communication path to the target system. figure 32 shows the connections required for this setup. figure 31: data flow diagram of mpu to cfgjtag tsttdi ta p ctrl. tsttdo tdo tdi cfgtdo cfgtdi tdi tdo tdi tdo tdo tdi ds080_30_030801 *cfcgtck and cfgtms lines are driven by ace controller core logic and are broadcast to all target devices. bs n a c mpu compactflash ace controller core (test jtag port) (configuration jtag port) system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 49 advance product specification 1-800-255-7778 r write data to cfgjtag interface control flow process the target devices in the cfgjtag chain can also be pro- grammed via the mpu interface as shown in figure 33 . the first step is to arbitrate for the data buffer by requesting a compactflash lock as shown in figure 24 . once the lock has been granted, the following steps should be taken to write configuration data to the cfgjtag controller: 1. reset the cfgjtag controller by setting the cfgreset bit (bit 7) of the controlreg register (mpu address 18h) to a 1. 2. select the mpu interface as the source of the configuration data by setting the cfgsel bit (bit 6) of the controlreg register (mpu byte address 18h) to a 1. 3. direct the cfgjtag controller to wait for the mpu interface for the start signal by setting the both the forcecfgmode (bit 3) and cfgmode (bit 4) bits of the controlreg register (mpu byte address 18h) to a 1. 4. set the configuration start signal by setting the cfgstart bit (bit 5) of the controlreg register (mpu byte address 18h) to a 1. figure 32: wiring diagram of mpu to cfgjtag ace controller xilinx fpga target chain cfgtck cfgtms cfgtdo cfgtdi tck tms tdi tdo clk mpbrdy mpirq mpa(6:0) mpd(15:0) v cc v cc ds080_33_121201 mpu device refer to the microprocessor or microcontroller data sheet for appropriate signal names. cfginit cfgprog program init reset statled errled mpce mpwe mpoe 5.1 k ? v cc cfrsvd 180 ? 180 ? system ace compactflash solution 50 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r 5. take the cfgjtag controller out of reset by setting the cfgreset bit (bit 7) of the controlreg register (mpu address 18h) to a 0. 6. at this point, the configuration data should be written to the data buffer (as shown in figure 30 ) until configuration is done or until an error is encountered. note that in either case that an entire buffer ? s worth of data should be written to the buffer to ensure that it gets sent to the cfgjtag controller. after the configuration information has been written suc- cessfully, the cfgdone bit (bit 7) of the statusreg reg- ister (mpu byte address 04h) should be set to a 1. if this is not the case, then the other bits of the statusreg and errorreg register should indicate the status of the con- figuration process. figure 33: write data to cfgjtag interface control flow process read status & error bits at byte addresses 04h through 0bh initialize buffer count variable* write data buffer return error. decrement buffer count variable no yes *set buffer count variable equal to the number of buffers in a transfer write data to cfgjtag set cfgsel bit to a 1 at byte address 18h select mpu as config data source set cfgreset bit to a 0 at byte address 18h clear configuration controller reset get cf lock set forcecfgmode bit to a 1 at byte address 18h set cfgmode bit to a 0 at byte address 18h direct controller to wait for mpu set cfgreset bit to a 1 at byte address 18h reset configuration controller set cfgstart bit to a 1 at byte address 18h start configuration buffer count equal to 0? check status of configuration error? data written. return status. no yes ds080_55_051701 system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 51 advance product specification 1-800-255-7778 r test jtag (tstjtag) to configuration jtag (cfgjtag) setup this setup provides a 1149.1 boundary-scan communication path to the target fpga system. using this setup, the target system can be configured via jtag from a jtag compliant tool. figure 34: data flow diagram of tstjtag to cfgjtag (using bypass path) tsttdi ta p ctrl. tsttdo tdo tdi cfgtdo cfgtdi tdi tdo tdi tdo tdo tdi ds080_32_030801 *cfcgtck and cfgtms lines are driven by ace controller core logic and are broadcast to all target devices. bs n a c mpu compactflash ace controller core (test jtag port) (configuration jtag port) figure 35: data flow diagram of tstjtag to cfgjtag (using boundary-scan path) tsttdi ta p ctrl. tsttdo tdo tdi cfgtdo cfgtdi tdi tdo tdi tdo tdo tdi ds080_34_051701 *tsttck, tsttms are multiplexed onto the cfgtck, cfgtms lines, respectively and are brodcast to all devices. bs n a c mpu compactflash ace controller core (test jtag port) (configuration jtag port) system ace compactflash solution 52 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r the ace controller handles all necessary steps to perform a configuration from the tstjtag to the target system via the cfgjtag interface. when using the tstjtag to cfgjtag setup, the signals in figure 36 should be connected. figure 36: wiring diagram of tstjtag to cfgjtag test jtag interface ace controller configuration jtag interface (xilinx fpga target chain) tck tms tck tdi tdo cfgtms cfgtck cfgtdo cfgtdi tms tdi tdo tsttck tsttms tsttdi tsttdo v cc v cc ds080_35_121201 reset cfginit cfgprog program init reset cfrsvd statled errled v cc 5.1 k ? 180 k ? 180 k ? system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 53 advance product specification 1-800-255-7778 r general timing specifications mpu interface timing characteristics table 28: clock frequency characteristics symbol parameter min max units f (clk) system ace clock frequency 33 mhz f (tsttck) test jtag clock frequency 16.7 mhz table 29: mpu interface timing characteristics symbol parameter min max units t s(mpaclk) mpa[6:0] setup time before rising edge of clk 4 ns t s(mpceclk) mpce setup time before rising edge of clk 4 ns t s(mpdclk) mpd[15:0] setup time before rising edge of clk 4 ns t s(mpoeclk) mpoe setup time before rising edge of clk 12 ns t s(mpweclk) mpwe setup time before rising edge of clk 12 ns t h(clkmpa) mpa hold time after rising edge of clk 0 ns t h(clkmpce) mpce hold time after rising edge of clk 0 ns t h(clkmpd) mpd[15:0] hold time after rising edge of clk 0 ns t h(clkmpoe) mpoe hold time after rising edge of clk 0 ns t h(clkmpwe) mpwe hold time after rising edge of clk 0 ns t d(clkmpd) clk rising edge to mpd 22 ns t d(clkmpbrdy) clk rising edge to mpbrdy 22 ns t d(clkmpirq) clk rising edge to mpirq 22 ns t d(mpcempd) propagation delay from mpce to mpd 13 ns t d(mpoempd) propagation delay from mpoe to mpd 13 ns system ace compactflash solution 54 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r compactflash interface timing characteristics configuration jtag interface timing characteristics table 30: compactflash interface timing characteristics symbol parameter min max units t s(cfcdclk) cfcd1 and cfcd2 setup time before rising edge of clk 4 ns t s(cfdclk) cfd[15:0] setup time before rising edge of clk 4 ns t s(cfwaitclk) cfwait setup time before rising edge of clk 4 ns t h(clkcfcd) cfcd1 and cfcd2 hold time after rising edge of clk 0 ns t h(clkcfd) cfd[15:0] hold time after rising edge of clk 0 ns t h(clkcfwait) cfwait hold time after rising edge of clk 0 ns t d(clkcfa) clk rising edge to cfa[10:0] 19 ns t d(clkcfce) clk rising edge to cfce1 and cfce2 16 ns t d(clkcfd) clk rising edge to cfd[15:0] 19 ns t d(clkcfoe) clk rising edge to cfoe 16 ns t d(clkcfwe) clk rising edge to cfwe 16 ns table 31: configuration jtag interface timing characteristics symbol parameter min max units t s(cfgaddrclk) cfgaddr[2:0] setup time before rising edge of clk 6 ns t s(cfginitclk) cfginit setup time before rising edge of clk 11 ns t s(cfgmodepinclk) cfgmodepin setup time before rising edge of clk 7 ns t s(cfgtdiclk) cfgtdi setup time before falling edge of clk 4 ns t h(clkcfgaddr) cfgaddr[2:0] hold time after rising edge of clk 0 ns t h(clkcfginit) cfginit hold time after rising edge of clk 0 ns t h(clkcfgmodepin) cfgmodepin hold time after rising edge of clk 0 ns t h(clkcfgtdi) cfgtdi hold time after falling edge of clk 0 ns t d(clkcfgprog) clk rising edge to cfgprog 17 ns t d(clkcfgtdo) clk falling edge to cfgtdo 16 ns t d(clkcfgtms) clk falling edge to cfgtms 20 ns t d(clkcfgtck) propagation delay from clk to cfgtck 15 ns system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 55 advance product specification 1-800-255-7778 r test jtag interface timing characteristics miscellaneous timing characteristics table 32: test jtag interface timing characteristics symbol parameter min max units t s(tsttditsttck) tsttdi setup time before rising edge of tsttck 4 ns t s(tsttmststtck) tsttms setup time before rising edge of tsttck 4 ns t s(intsttck) all other inputs setup time before rising edge of tsttck 5 ns t h(tsttcktsttdi) tsttdi hold time after rising edge of tsttck 0 ns t h(tsttcktsttms) tsttms hold time after rising edge of tsttck 0 ns t h(tsttckin) all other inputs hold time after rising edge of tsttck 0 ns t d(tsttckout) tsttck falling edge to all other outputs 24 ns t d(tsttckcfgtck) propagation delay from tsttck to cfgtck 14 ns t d(cfgtditsttdo) propagation delay from cfgtdi to tsttdo 11 ns t d(tsttmscfgtms) propagation delay from tsttms to cfgtms 13 ns table 33: miscellaneous timing characteristics symbol parameter min max units t s(resetclk) reset setup time before rising edge of clk 7 ns t h(clkreset) reset hold time after rising edge of clk 0 ns t h(clkerrled) clk rising edge to errled 17 ns t h(clkstatled) clk rising edge to statled 17 ns system ace compactflash solution 56 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r electrical characteristics for more detailed ace flash specifications, refer to the compactflash memory card product manual from sandisk, or visit their website at: www.sandisk.com . table 34: ace flash card characteristics type description symbol min typ max units conditions dc input voltage v cc ? 0.3 7.0 v 1 input voltage (v cc = 3.3 v) v ih v il 2.4 0.6 v 2 input voltage (v cc = 3.3 v) v ih v il 1.5 0.6 v 3 input voltage (v cc = 3.3 v) v th v tl 1.8 1.0 v 1 output voltage v oh v ol v cc ? 0.8 gnd + 0.4 vi oh = ? 4 ma i ol = 4 ma 2 output voltage v oh v ol v cc ? 0.8 gnd + 0.4 vi oh = ? 8 ma i ol = 8 ma 3 output voltage v oh v ol v cc ? 0.8 gnd + 0.4 vi oh = ? 8 ma i ol = 8 ma x 3-state leakage current i oz ? 10 10 a v ol = gnd v oh = v cc ambient temperature t a 060 c ixz il input leakage current ? 1 1 a v ih = v cc /v il = gnd ixu rpu1 pull-up resistor 50 500 k 8 v cc = 5.0 v ixd rpd1 pull-down resistor 50 500 k 8 v cc = 5.0 v o tx to t e m p o l e i oh & i ol o zx 3-state n-p channel i oh & i ol o px p-channel only i oh only o nx n-channel only i ol only notes: 1. the minimum pull-up resistor leakage current meets the pcmcia specification of 10 k 8 but is intentionally higher in the compactflash memory card series product to reduce power use. x refers to the type 1, 2, or 3. for example, ot3 refers to totempole output with a type 3 output drive characteristic. system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 57 advance product specification 1-800-255-7778 r table 35: ace controller absolute maximum ratings (for v ccl = 2.5 [v] or v ccl = 3.3 [v]) description symbol limits units power supply voltage v cch (1) gnd ? 0.3 to 7.0 v v ccl (1) gnd ? 0.3 to 4.0 input voltage v ih gnd ? 0.3 to v cch + 0.5 v v il gnd ? 0.3 to v ccl + 0.5 output voltage v oh gnd ? 0.3 to v cch + 0.5 v v ol gnd ? 0.3 to v ccl + 0.5 output current/pin i out 30 ma storage temperature t stg ? 65 to 150 c notes: 1. v cch is greater than or equal to v ccl . table 36: ace controller recommended operating conditions (for v ccl = 2.5 [v]) description symbol min typ max units power supply voltage v cch 3.0 3.3 3.6 v v ccl 2.25 2.5 2.75 input voltage v ih gnd ? v cch v v il gnd ? v ccl ambient temperature t a ? 40 ? 85 (1) c notes: 1. the ambient temperature range is recommended for t j = ? 40 to 125 c. table 37: ace controller recommended operating conditions (for v ccl = 3.3 [v]) description symbol min typ max units power supply voltage v cch 3.0 3.3 3.6 v v ccl 3.0 3.3 3.6 input voltage v ih gnd ? v cch v v il gnd ? v ccl ambient temperature t a ? 40 ? 85 (1) c notes: 1. the ambient temperature range is recommended for t j = ? 40 to 125 c. system ace compactflash solution 58 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r table 38: ace controller characteristics description symbol min typ max units conditions quiescent current (between v cch and gnd) i ccsh -- -- 300 a v i = v cch or v ccl or gnd, v cch = max, v ccl = max, i oh = i ol = 0 quiescent current (between v ccl and gnd) i ccsl -- -- 420 a v i = v cch or v ccl or gnd, v cch = max, v ccl = max, i oh = i ol = 0 input leakage current i li ? 1-- 1a v cch = max, v ccl = max, v ihh = v cch , v ihl = v ccl , v il = gnd high-level input voltage v ih1h 2.0 -- -- v input characteristics for i/o supply rail v cch = max low-level input voltage v il1h -- -- 0.8 v input characteristics for i/o supply rail v cch = min high-level input voltage v ih1l 2.0 -- -- v input characteristics for i/o supply rail v ccl = max low-level input voltage v il1l -- -- 0.8 v input characteristics for i/o supply rail v ccl = min pull-up resistance r pu1h 40 100 240 k 8 v i = gnd pull-down resistance r pd1h 40 100 240 k 8 v i = v cch pull-up resistance r pu1l 20 50 120 k 8 v i = gnd pull-down resistance r pd1l 20 50 120 k 8 v i = v ccl high-level output voltage v oh3h v cch ? 0.4 -- -- v v cch = min, i oh = ? 12 ma low-level output voltage v ol3h -- -- gnd + 0.4 v v cch = min, i ol = 12 ma high-level output voltage v oh3l v ccl ? 0.4 -- -- v v ccl = min, i oh = ? 12 ma low-level output voltage v ol3l -- -- gnd + 0.4 v v ccl = min, i ol = 12 ma off-state leakage current i oz ? 1-- 1a v cch = max, v ccl = max, v ohh = v cch, v ohl = v ccl, v ol = gnd input terminal capacitance c i -- -- -- pf -- output terminal capacitance c o -- -- -- pf -- input/output terminal capacitance c io -- -- -- pf -- system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 59 advance product specification 1-800-255-7778 r package specifications: (package dimensions and reliability data) figure 37: ace flash card dimensions 1.685.004 [42.80] 1.433 .006 [36.40] .039.002 [1.00] .063.002 [1.60] 1 26 25 50 .040.003 [1.00] .040.003 [1.00] .130.004 [3.30] 2x 1.015 .003 [25.78] 2x .472 .004 [12.00] 2x .118 .003 [3.00] top 1.640.005 [41.66] .096.003 [2.4] .030.003 [0.8] .025.003 [0.6] 4x r.020.004 [0.5] ds080_36_020601 system ace compactflash solution 60 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r ta b l e 3 9 shows ace flash reliability considerations. figure 38: ace flash card adapter dimensions 0.130 [3.3] 0.196 [5.0] 1.196 [30.4] 3.370 [85.6] 2.126 [54.0] 1.694 [43.03] 0.138 [3.5] .866 [22.0] 1.536 [39.03] .472 [12.0] .078 [2.0] ds080_37_020601 table 39: ace flash reliability mtbf (@ 25 degrees c) >1,000,000 hours preventative maintenance none data reliability <1 non-recoverable error in 10 14 bits read endurance >= 300,000 erase/program cycles per logical sector system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 61 advance product specification 1-800-255-7778 r figure 39: ace controller tq144 package drawing ds080_47_030801 system ace compactflash solution 62 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r pin descriptions this section provides ace flash and ace controller pinout information. ace flash card i/o pins ta b l e 4 0 lists ace flash signal/pin assignments. low active signals have an overline . pin types are input, output, or input/output. table 40: ace flash card pin assignments and pin types pc card memory mode pin number signal name pin type in, out (2) type 1 gnd ground 2 d03 i/o i1z,oz3 3 d04 i/o i1z,oz3 4 d05 i/o i1z,oz3 5 d06 i/o i1z,oz3 6 d07 i/o i1z,oz3 7ce1 ii3u 8 a10 i i1z 9oe ii3u 10 a09 i i1z 11 a08 i i1z 12 a07 i i1z 13 vcc power 14 a06 i i1z 15 a05 i i1z 16 a04 i i1z 17 a03 i i1z 18 a02 i i1z 19 a01 i i1z 20 a00 i i1z 21 d00 i/o i1z,oz3 22 d01 i/o i1z,oz3 23 d02 i/o i1z,oz3 24 wp o ot3 25 cd2 o ground 26 cd1 o ground 27 d11 (1) i/o i1z,oz3 28 d12 (1) i/o i1z,oz3 29 d13 (1) i/o i1z,oz3 30 d14 (1) i/o i1z,oz3 31 d15 (1) i/o i1z,oz3 32 ce2 (1) ii3u 33 vs1 oground 34 iord ii3u 35 iowr ii3u 36 we ii3u 37 rdy/bsy oot1 38 vcc power 39 csel ii2z 40 vs2 o open 41 reset i i2z 42 wait oot1 43 inpack oot1 44 reg ii3u 45 bvd2 i/o i1u,ot1 46 bvd1 i/o i1u,ot1 47 d08 (1) i/o i1z,oz3 48 d09 (1) i/o i1z,oz3 49 d10 (1) i/o i1z,oz3 50 gnd ground notes: 1. these signals are required only for 16-bit access and not required when installed in 8-bit systems. for lowest power dissipation, leave these signals open. 2. for definitions of in, out type, refer to electrical characteristics , page 56 . table 40: ace flash card pin assignments and pin types (continued) pc card memory mode pin number signal name pin type in, out (2) type system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 63 advance product specification 1-800-255-7778 r ta b l e 4 1 defines the dc characteristics for all ace flash input and output type structures. table 41: ace flash signal descriptions signal name dir. pin description a10 - a0 i 8, 10, 11, 12, 14, 15, 16, 17, 18, 19, 20 these address lines along with the reg signal are used to select the following: the i/o port address registers within the compactflash card, the memory mapped port address registers within the card, a byte in the card's information structure and its configuration control and status registers. bvd1 i/o 46 this signal is asserted high as the bvd1 signal since a battery is not used with this product. bvd2 i/o 45 this output line is always driven to a high state in memory mode since a battery is not required for this product. cd1 , cd2 o 26, 25 these card detect pins are connected to ground on the compactflash card. they are used by the host to determine if the card is fully inserted into its socket. ce1 , ce2 i 7, 32 these input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. ce2 always accesses the odd byte of the word. ce1 accesses the even byte or the odd byte of the word depending on a0 and ce2 . a multiplexing scheme based on a0, ce1 , ce2 allows 8 bit hosts to access all data on d0-d7. see the ? attribute memory function ? tables in the compactflash memory card product manual . csel i 39 this signal is not used for this mode. d15 - d00 i/o 31, 30, 29, 28, 27, 49, 48, 47, 6, 5, 4, 3, 2, 23, 22, 21 these lines carry the data, commands and status information between the host and the controller. d00 is the lsb of the even byte of the word. d08 is the lsb of the odd byte of the word. gnd -- 1, 50 ground. inpack o 43 this signal is not used in this mode. iord i 34 this signal is not used in this mode. iowr i 35 this signal is not used in this mode. oe i 9 this is an output enable strobe generated by the host interface. it is used to read data from the compactflash card in memory mode and to read the cis and configuration registers. rdy/bsy o 37 in memory mode this signal is set high when the compactflash card is ready to accept a new data transfer operation and held low when the card is busy. the host memory card socket must provide a pull-up resistor. at power up and at reset, the rdy/-bsy signal is held low (busy) until the compactflash card has completed its power up or reset function. no access of any type should be made to the compactflash card during this time. the rdy/-bsy signal is held high (disabled from being busy) whenever the following condition is true: the compactflash card has been powered up with reset continuously disconnected or asserted. system ace compactflash solution 64 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r ace controller i/o pins ta b l e 4 2 lists ace controller active pins. reg attribute memory select i 44 this signal is used during memory cycles to distinguish between common memory and register (attribute) memory accesses. high for common memory, low for attribute memory. reset i 41 when the pin is high, this signal resets the compactflash card. the card is reset only at power up if this pin is left high or open from power-up. the card is also reset when the soft reset bit in the card configuration option register is set. vcc -- 13, 38 +5 v, +3.3 v power. vs1 vs2 o 33 40 voltage sense signals. vs1 is grounded so that the compactflash card cis can be read at 3.3 volts and vs2 is open and reserved by pcmcia for a secondary voltage. wait o42 the wait signal is driven low by the compactflash card to signal the host to delay completion of a memory or i/o cycle that is in progress. we i 36 this is a signal driven by the host and used for strobing memory write data to the registers of the compactflash card when the card is configured in the memory interface mode. it is also used for writing the configuration registers. wp write protect o 24 memory mode ? the compactflash card does not have a write protect switch. this signal is held low after the completion of the reset initialization sequence. table 41: ace flash signal descriptions (continued) signal name dir. pin description table 42: ace controller pin table (in = input, out2 = 2-state output, out3 = 3-state output) pin name pin # i/o type i/o supply rail termination description clk 93 in v ccl n/a ace controller system clock reset 33 in v ccl int. pull-up ace controller reset (active low; needs to be active for three clock cycles) statled 95 out3 (open-drain) v ccl ext. pull-up ace controller status led errled 96 out3 (open-drain) v ccl ext. pull-up ace controller error led; when low, this pin indicates that an error has occurred in the ace controller. mpce 42 in v ccl int. pull-up chip enable (active low) mpwe 76 in v ccl int. pull-up write enable (active low) mpoe 77 in v ccl int. pull-up output enable (active low) mpirq 41 out2 v ccl n/a interrupt request flag mpbrdy 39 out2 v ccl n/a data buffer ready flag mpa00 70 in v ccl n/a mpu address line 0 mpa01 69 in v ccl n/a mpu address line 1 system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 65 advance product specification 1-800-255-7778 r mpa02 68 in v ccl n/a mpu address line 2 mpa03 67 in v ccl n/a mpu address line 3 mpa04 45 in v ccl n/a mpu address line 4 mpa05 44 in v ccl n/a mpu address line 5 mpa06 43 in v ccl n/a mpu address line 6 mpd00 66 in/out3 v ccl n/a mpu data line 0 mpd01 65 in/out3 v ccl n/a mpu data line 1 mpd02 63 in/out3 v ccl n/a mpu data line 2 mpd03 62 in/out3 v ccl n/a mpu data line 3 mpd04 61 in/out3 v ccl n/a mpu data line 4 mpd05 60 in/out3 v ccl n/a mpu data line 5 mpd06 59 in/out3 v ccl n/a mpu data line 6 mpd07 58 in/out3 v ccl n/a mpu data line 7 mpd08 56 in/out3 v ccl n/a mpu data line 8 mpd09 53 in/out3 v ccl n/a mpu data line 9 mpd10 52 in/out3 v ccl n/a mpu data line 10 mpd11 51 in/out3 v ccl n/a mpu data line 11 mpd12 50 in/out3 v ccl n/a mpu data line 12 mpd13 49 in/out3 v ccl n/a mpu data line 13 mpd14 48 in/out3 v ccl n/a mpu data line 14 mpd15 47 in/out3 v ccl n/a mpu data line 15 cfa00 4 out2 v cch n/a compactflash address line 0 cfa01 142 out2 v cch n/a compactflash address line 1 cfa02 141 out2 v cch n/a compactflash address line 2 cfa03 139 out2 v cch n/a compactflash address line 3 cfa04 137 out2 v cch n/a compactflash address line 4 cfa05 135 out2 v cch n/a compactflash address line 5 cfa06 134 out2 v cch n/a compactflash address line 6 cfa07 132 out2 v cch n/a compactflash address line 7 cfa08 130 out2 v cch n/a compactflash address line 8 cfa09 125 out2 v cch n/a compactflash address line 9 cfa10 121 out2 v cch n/a compactflash address line 10 cfd00 5 in/out3 v cch n/a compactflash data line 0 cfd01 6 in/out3 v cch n/a compactflash data line 1 cfd02 8 in/out3 v cch n/a compactflash data line 2 table 42: ace controller pin table (in = input, out2 = 2-state output, out3 = 3-state output) (continued) pin name pin # i/o type i/o supply rail termination description system ace compactflash solution 66 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r cfd03 104 in/out3 v cch n/a compactflash data line 3 cfd04 106 in/out3 v cch n/a compactflash data line 4 cfd05 113 in/out3 v cch n/a compactflash data line 5 cfd06 115 in/out3 v cch n/a compactflash data line 6 cfd07 117 in/out3 v cch n/a compactflash data line 7 cfd08 7 in/out3 v cch n/a compactflash data line 8 cfd09 11 in/out3 v cch n/a compactflash data line 9 cfd10 12 in/out3 v cch n/a compactflash data line 10 cfd11 105 in/out3 v cch n/a compactflash data line 11 cfd12 107 in/out3 v cch n/a compactflash data line 12 cfd13 114 in/out3 v cch n/a compactflash data line 13 cfd14 116 in/out3 v cch n/a compactflash data line 14 cfd15 118 in/out3 v cch n/a compactflash data line 15 cfce1 119 out2 v cch n/a compactflash chip enable 1 (active low); cfce2 138 out2 v cch n/a compactflash chip enable 2 (active low); cfreg 3out2 v cch n/a compactflash register select line (active low); this pin is always driven to a 1 but is provided here for future compatibility. cfwe 131 out2 v cch n/a compactflash write enable line (active low) cfoe 123 out2 v cch n/a compactflash output enable line (active low) cfwait 140 in v cch n/a compactflash memory cycle wait flag (active low) cfrsvd 133 in v cch ext. pull-up this pin must be pulled up to v cch using an external pull-up resistor. cfcd1 103 in v cch int. pull-up compactflash card detect line 1 (active low) cfcd2 13 in v cch int. pull-up compactflash card detect line 2 (active low) cfgaddr0 86 in v ccl int. pull-down configuration address select pin 0 cfgaddr1 87 in v ccl int. pull-down configuration address select pin 1 cfgaddr2 88 in v ccl int. pull-down configuration address select pin 2 cfgmodepin 89 in v ccl int. pull-up configuration mode pin: when 0, this pin instructs the ace controller to start the configuration process when the cfgstart bit is set in the controlreg register in the mpu interface. when 1, this pin instructs the ace controller to start the configuration process immediately following reset. tsttdi 102 in v cch int. pull-up test jtag port test data input tsttck 101 in v cch n/a test jtag port test clock table 42: ace controller pin table (in = input, out2 = 2-state output, out3 = 3-state output) (continued) pin name pin # i/o type i/o supply rail termination description system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 67 advance product specification 1-800-255-7778 r tsttms 98 in v cch int. pull-up test jtag port test mode select tsttdo 97 out3 v cch ext. pull-up (1) test jtag port test data output cfgtdo 82 out3 v ccl ext. pull-up (1) configuration jtag test data output cfgtdi 81 in v ccl int. pull-up configuration jtag test data input cfgtck 80 out2 v ccl n/a configuration jtag test clock cfgtms 85 out3 v ccl ext. pull-up (1) configuration jtag test mode select cfgprog 79 out3 (open-drain) v ccl ext. pull-up configuration jtag program pin (active low); this pin is driven low when the ace controller prog instruction is executed. cfginit 78 in v ccl int. pull-up configuration jtag init pin (active low); this pin is used to sense when all devices are ready to be programmed (i.e., init = 1 indicates target device(s) are ready to receive configuration data and init = 0 indicates that the target device(s) are being cleared and are not ready to be configured) por_bypass 108 in v cch int. pull-down power-on-reset (por) bypass input; used in conjunction with por_reset to bypass the internal por circuit in favor of using an external board-level por circuit; the internal por circuit is bypassed when por_bypass = 1; the por_bypass pin should be held at a static 0 or 1 while the ace controller is receiving power. por_reset 72 in v cch int. pull-down power-on-reset bypass input; can be used in conjunction with por_bypass to bypass the internal por circuit in favor of using an external board-level por circuit; all internal circuitry is reset when por_bypass = 1 and por_reset = 1; the por_reset pulse duration should be at least 1 microsecond long. por_test 74 out2 v cch n/a power-on-reset test output; this pin should be a true ? no connect ? on the board. this pin is low when it is finished resetting. notes: 1. jtag 1149.1 requires a pull-up resistor on potentially undriven tdo/tms signals. table 42: ace controller pin table (in = input, out2 = 2-state output, out3 = 3-state output) (continued) pin name pin # i/o type i/o supply rail termination description system ace compactflash solution 68 www.xilinx.com ds080 (v1.4) january 3, 2002 1-800-255-7778 advance product specification r ta b l e 4 3 lists ace controller voltage and ground pins. ta b l e 4 4 lists ace controller no-connect pins. table 43: ace controller voltage and ground pins pin name pin number description vcch 1 high-voltage (3.3v) source pins 17 37 55 73 92 109 128 vccl 10 low-voltage (2.5v or 3.3v) source pins 15 25 57 84 94 99 126 gnd 9 ground pins 18 26 35 46 54 64 75 83 91 100 110 111 112 120 129 136 144 table 44: ace controller no-connect pins pin name pin number description nc 2 pins that must not be connected to any board-level signals, including ground and power planes. 14 16 19 20 21 22 23 24 27 28 29 30 31 32 34 36 38 40 71 90 122 124 127 143 system ace compactflash solution ds080 (v1.4) january 3, 2002 www.xilinx.com 69 advance product specification 1-800-255-7778 r ordering information revision history system ace valid ordering combinations description package operating range xccace ? tq144i ace controller chip tq144 (t a = -40 to +85 c) XCCACE128-I 128-mbit ace flash card cf type i (t a = -40 to +85 c) xccace256-i 256-mbit ace flash card cf type i (t a = -40 to +85 c) version no. date description 1.0 05/18/01 initial xilinx release. 1.1 06/04/01 corrected table 27, page 35 . cfgmode is 1 after reset, 0 after mpu start signal. 1.2 07/18/01 updated. 1.3 12/12/01 updated. 1.4 01/03/02 updated ta bl e 2 , figure 20 , figure 22 , figure 32 , figure 36 , and ta bl e 4 2 (last row only). |
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